The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method and structure for relieving transistor performance degradation due to shallow trench isolation (STI) induced stresses.
Integrated circuits having transistors in close proximity to each other can often exhibit unintended current leakage between adjacent transistors. As a result, various isolation techniques have been developed to reduce such leakage currents. For example, STI is one conventional approach frequently used to reduce leakage currents for integrated circuits having nominal feature sizes of about 90 nanometers (nm) or smaller. STI entails the creation of trenches within a substrate (e.g., silicon, silicon-on-insulator, etc.) located between adjacent transistors. The trenches are then filled with a dielectric material, such as silicon dioxide, for example, so as to provide a barrier that impedes the flow of leakage current between the transistors on opposite sides of the trench.
Unfortunately, the use of STI structures can create undesirable stresses on the channels of adjacent transistors, depending upon the channel type, doping level, width, and length of adjacent transistors, as well as the spacing between the channel and the trench and the spacing between additional trenches. This stress is generally most pronounced in low voltage transistors (e.g., transistors having an operating voltage in the range of approximately 1.2 volts to 3.3 volts). In such low voltage transistors, a compressive STI stress can cause reduced electron mobility and increased hole mobility, thus resulting in slightly enhanced p-type metal oxide semiconductor (PMOS) performance but significantly degraded n-type metal oxide semiconductor NMOS performance. Regardless, the net effect of such changes is slower performance of integrated circuits such as, for example, complementary metal oxide semiconductor (CMOS) circuits.
In the past, STI stress was less of an issue because of the relative large size of the gate oxide areas and device size in general. However, as device sizes continue to shrink, the spacing between the STI and the transistor channel is reduced. As a result, the performance degradation becomes more severe. For example, in 65 nm technology, NFET device performance is degraded by about 12% or more due to compressive stress. Accordingly, it would be desirable to be able to alleviate STI stress related performance degradation for integrated circuit (IC) devices having conventionally formed STI regions.